SystemVerilog_3.1a Language Reference Manual
ThisdocumentspecifiestheAccelleraextensionsforahigherlevelofabstractionformodelingandverificationwiththeVerilogHardwareDescriptionLanguage.TheseadditionsextendVerilogintothesystemsspaceandtheverificationspace.SystemVerilogisbuiltontopoftheworkoftheIEEEVer
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用户评论
可以作为SV语言的参考资料，很规范，很详尽
比较全，但是是全英文的