山东建筑大学计算机学院数字电路期末考试重点资料

本资料包含多种考试重点代码和3-8译码器示例，供同学们参考使用。3-8译码器的代码如下：

library ieee;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

ENTITY decoder3to8 IS

PORT( A2,A1,A0,E3,E2,E1 : IN STD_LOGIC;

Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0: OUT STD_LOGIC);

END ENTITY decoder3to8;

ARCHITECTURE BHV OF decoder3to8 IS

SIGNAL A: STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL Y: STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

A <= A2 & A1 & A0;

PROCESS ( A,E3,E2,E1)

BEGIN

IF((E1 = '1') and (E2 = '0') and (E3 = '0')) then

CASE (A) IS

WHEN "000" => Y <= "10000000";

WHEN "001" => Y <= "01000000";

WHEN "010" => Y <= "00100000";

WHEN "011" => Y <= "00010000";

WHEN "100" => Y <= "00001000";

WHEN "101" => Y <= "00000100";

WHEN "110" => Y <= "00000010";

WHEN "111" => Y <= "00000001";

END CASE;

END IF;

Y0 <= Y(0);

Y1 <= Y(1);

Y2 <= Y(2);

Y3 <= Y(3);

Y4 <= Y(4);

Y5 <= Y(5);

Y6 <= Y(6);

Y7 <= Y(7);

END PROCESS;

END BHV;