Verilog HDL语言:指南数字设计与合成(第二版)

Part1.BasicVerilogTopics

Chapter1.OverviewofDigitalDesignwithVerilogHDL

SecTIon1.1.EvoluTIonofComputer-AidedDigitalDesign

SecTIon1.2.EmergenceofHDLs

SecTIon1.3.TypicalDesignFlow

Section1.4.ImportanceofHDLs

Section1.5.PopularityofVerilogHDL

Section1.6.TrendsinHDLs

Chapter2.HierarchicalModelingConcepts

Section2.1.DesignMethodologies

Section2.2.4-bitRippleCarryCounter

Section2.3.Modules

Section2.4.Instances

Section2.5.ComponentsofaSimulation

Section2.6.Example

Section2.7.Summary

Section2.8.Exercises

Chapter3.BasicConcepts

Section3.1.LexicalConventions

Section3.2.DataTypes

Section3.3.SystemTasksandCompilerDirectives

Section3.4.Summary

Section3.5.Exercises

Chapter4.ModulesandPorts

Section4.1.Modules

Section4.2.Ports

Section4.3.HierarchicalNames

Section4.4.Summary

Section4.5.Exercises

Chapter5.Gate-LevelModeling

Section5.1.GateTypes

Section5.2.GateDelays

Section5.3.Summary

Section5.4.Exercises

Chapter6.DataflowModeling

Section6.1.ContinuousAssignments

Section6.2.Delays

Section6.3.Expressions,Operators,andOperands

Section6.4.OperatorTypes

Section6.5.Examples

Section6.6.Summary

Section6.7.Exercises

Chapter7.BehavioralModeling

Section7.1.StructuredProcedures

Section7.2.ProceduralAssignments

Section7.3.TimingControls

Section7.4.ConditionalStatements

Section7.5.MultiwayBranching

Section7.6.Loops

Section7.7.SequentialandParallelBlocks

Section7.8.GenerateBlocks

Section7.9.Examples

Section7.10.Summary

Section7.11.Exercises

Chapter8.TasksandFunctions

Section8.1.DifferencesbetweenTasksandFunctions

Section8.2.Tasks

Section8.3.Functions

Section8.4.Summary

Section8.5.Exercises

Chapter9.UsefulModelingTechniques

Section9.1.ProceduralContinuousAssignments

Section9.2.OverridingParameters

Section9.3.ConditionalCompilationandExecution

Section9.4.TimeScales

Section9.5.UsefulSystemTasks

Section9.6.Summary

Section9.7.Exercises

Part2.AdvancedVerilogTopics

Chapter10.TimingandDelays

Section10.1.TypesofDelayModels

Section10.2.PathDelayModeling

Section10.3.TimingChecks

Section10.4.DelayBack-Annotation

Section10.5.Summary

Section10.6.Exercises

Chapter11.Switch-LevelModeling

Section11.1.Switch-ModelingElements

Section11.2.Examples

Section11.3.Summary

Section11.4.Exercises

Chapter12.User-DefinedPrimitives

Section12.1.UDPbasics

Section12.2.CombinationalUDPs

Section12.3.SequentialUDPs

Section12.4.UDPTableShorthandSymbols

Section12.5.GuidelinesforUDPDesign

Section12.6.Summary

Section12.7.Exercises

Chapter13.ProgrammingLanguageInterface

Section13.1.UsesofPLI

Section13.2.LinkingandInvocationofPLITasks

Section13.3.InternalDataRepresentation

Section13.4.PLILibraryRoutines

Section13.5.Summary

Section13.6.Exercises

Chapter14.LogicSynthesiswithVerilogHDL

Section14.1.WhatIsLogicSynthesis?

Section14.2.ImpactofLogicSynthesis

Section14.3.VerilogHDLSynthesis

Section14.4.SynthesisDesignFlow

Section14.5.VerificationofGate-LevelNetlist

Section14.6.ModelingTipsforLogicSynthesis

Section14.7.ExampleofSequentialCircuitSynthesis

Section14.9.Exercises

Chapter15.AdvancedVerificationTechniques

Section15.1.TraditionalVerificationFlow

Section15.2.AssertionChecking

Section15.3.FormalVerification

Section15.4.Summary

Part3.Appendices

AppendixA.StrengthModelingandAdvancedNetDefinitions

SectionA.1.StrengthLevels

SectionA.2.SignalContention

SectionA.3.AdvancedNetTypes

AppendixB.ListofPLIRoutines

SectionB.1.Conventions

SectionB.2.AccessRoutines

SectionB.3.Utility(tf_)Routines

AppendixC.ListofKeywords,SystemTasks,andCompilerDirectives

SectionC.1.Keywords

SectionC.2.SystemTasksandFunctions

SectionC.3.CompilerDirectives

AppendixD.FormalSyntaxDefinition

SectionD.1.SourceText

 Section D.2.  Declarations

Section D.3.  Primitive Instances

Section D.4.  Module and Generated Instantiation

Section D.5.  UDP Declaration and Instantiation

Section D.6.  Behavioral Statements

Section D.7.  Specify Section

Section D.8.  Expressions

Section D.9.  General

Endnotes 

Appendix E.  Verilog Tidbits

Origins of Verilog HDL

Interpreted, Compiled, Native Compiled Simulators

Event-Driven Simulation, Oblivious Simulation

Cycle-Based Simulation

Fault Simulation

General Verilog Web sites

Architectural Modeling Tools

High-Level Verification Languages

Simulation Tools

Hardware Acceleration Tools

In-Circuit Emulation Tools

Coverage Tools

Assertion Checking Tools

Equivalence Checking Tools

Formal Verification Tools

Appendix F.  Verilog Examples

Section F.1.  Synthesizable FIFO Model

Section F.2.  Behavioral DRAM Model

Bibliography

Manuals

Books

Quick Reference Guides

About the CD-ROM

Using the CD-ROM

Technical Support