USB的VHDL实现源码 library IEEE; use IEEE.STD_LOGIC_1164.all; package usbTSTPAK is -------------------- component usbTSTctrl port( signal sim: in STD_LOGIC; -- TRUE while simulating signal stim: in STD_LOGIC; -- TRUE to stimulate UUT -- signal clk48: out STD_LOGIC; --
怎么用呀。。。现在糊里糊涂的