verilog语法执行的顺序问题

always @ (negedge clk or negedge rst_n) if(!rst_n) begin out2 <= 1'b0; cnt <= 2'd0; end else begin cnt <= cnt + 1'b1; if(cnt == 2'd1) out2 <= ~out2; else if(cnt == 2'd2) begin cnt <= 2'd0; out2 <= ~out2; end end 比