STM32 F3产品技术培训 16.供电模块及功耗模式.pdf

STM32 F3产品技术培训-16.供电模块及功耗模式SRM32F30X Power Supply sPower Supply SchemesVDD=2.0 to 3.6V: External Power Supply forVppa domainlOsor VDD=1.8+/-8%:%: External PowerAD converterSupply for l/Os with internal regulator is OFF)D/A converterCOMPTemp. sensorDDAReset blockSSAVDDa=2.0 to 3.6 V: External Analog PowerPLLsupplies for ADC, DAC, Reset blocks, RCs andVon domainVa domainPLL10 RingsSTANDBY circuiti DAC working only if VDDa >=2. 4V(Wake-up logicWWWDG, RTC, LSECoreVBAT =1.65V to 3.6 V: For Backup domaincrystal 32K osc,MemoriesRCC CSRDigitalwhen VDD is not present.peripheralsVoltage RegulatorPower pins connection:VDD and Vdda can be provided by a separated powerLow Voltage detectorsupply sourceBackup domainVSS and Vssa must be tight to groundLSE crystal 32K oscBATBKP registersRCC BDCR registerRTClife. augmentedSRM32F37X Power Supply aPower Supply Schemesdpa domainVDD=2.0 to 3.6 V: External Power Supply forl/Os(or VDD=1. 8+/-8%: % External PowerAD converterSupply for l/Os with internal regulator is OFF.)DIA converterSDADC12Vn■COMPSDADC3 VppTemp. sensorSDADC123VssReset blockPLLVDDa= 2.0 to 3.6 V: External Analog powerSDADCSsupplies for ADC, DAC, Reset blocks, Rcs andssA口PLLdp domainVa domaini ADC and dac working only if VDDA >=2.4 V1/0 RingsSTANDBY circuitryVBaT =1.65V to 3.6 V: For Backup domain when(Wake-up logic,WWWDG. RTC, LSECoreVDD is not presentcrystal 32K osc,MemoriesRCC CSR)DigitaSDADCX_ VDD=2. 2 to 3.6V: External AnalogperipheralsPower supplies for SDADCs withVoltage RegulatorPower pins connection:Low Voltage detectorVDD and Vdda can be provided by a separated powerBackup domainsupply sourceLSE crystal 32K OScBKP registersVSS, VSSA and SDADCX VSS must be tight to groundBATRCC BDCR registerThe sd1 sd2 vdd and sd3 vdd can be different from vddRTCVDDa and from one anotherlife. augmentedPower Sequence 5When VDd power supply source is different from VDDa powersupply source(VDD< VDDA)The VDDa voltage level must be always greater or equal to theVDD VOltageDuring power-on, the VDDA must be provided first(before VDD)During power-off, it is allowed to have temporarily VDD> VDDA, butthe voltage difference must be <0. 4Vcould be maintained by an external Schottky diodeWhen SDADCX power supply is different from VDDA, VDDpower supply and from one anotherSDADCX VDD Threshold7 Can be used to generate a warningmessage and/or put the mcu into a safestatelife. augmentedBackup Domain gBackup Domain containsLow power calendar rtc (Alarm, periodic wakeup fromStop/Standby)64 and 128 Bytes Data rtc registers in STM32F30Xand sTM32F37x respectivelySeparate 32kHz OSc LSE) for RTCBackup DomainRCC BDCR register RTC clock source selection andenable LSE configpower switchRCC BDCR32KHZ OScSEReset only by rtc domain rESetWakeupWWDGLogicVBAT independent voltage supplyRTC TAMPXRTC+ 64(or 128 )Bytes DataAutomatic switch-over to VBaT when Vdd goes lowerthan pdr levelNo current sunk on VBAT When VDD present2 X Tamper events detection: resets all user backupregistersTime stamp event detectionlife. augmentedLoW Power Modes(1/4)1oSLEEP Mode: Core stopped, peripherals kept runningEntered by executing special instructionsWFI (Wait For InterruptExit: any peripheral interrupt acknowledged by the Nested Vectored Interrupt Controller(NVIC)WFE (Wait For Event)An event can be an interrupt enabled in the peripheral control register but NoT in the Nvic or an EXTIline configured in event modeExit: as soon as the event occurs No time wasted in interrupt entry/exitTwo mechanisms to enter this modeSleep Now: MCU enters SLEEP mode as soon as WFI/FE instruction are executedSleep on Exit: MCU enters SLEEP mode as soon as it exits the lowest priority ISRTo further reduce power consumption you can save power of unusedperipherals by gating their clocklife. augmented