A 10Gb/s CMOS Clock and Data Recovery Circuit
Thispaperdescribesthedesignofthefirst10-Gb/sCMOSclockanddatarecovery(CDR)circuit.Alinearphasedetector(PD)isintroducedthatcomparesthephaseoftheincomingdatawiththatofahalf-rateclock.TheCDRcircuitalsoincorporatesathree-stageinterpolatingringoscillatortoachieveawidetuningrange.
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