verilog—LCD1602

verilog—LCD1602代码：module lcd1602(clk,rst,lcd_rs,clklcd,lcd_rw,data); input clk,rst; output lcd_rs,lcd_rw,clklcd; output[7:0] data; reg lcd_rs,lcd_rw; reg[5:0] address; wire clk_16; reg[3:0] count; reg[15:0] clkcnt; reg tc_clkcnt; reg clklcd; reg clkint;