[book] nano-cmos design for manufacturabililty -- robust circuit and physical de

Abstract: 1 Introduction 1 1.1 Value of Design for Manufacturability / 1 1.2 Defi ciencies in Boolean-Based Design Rules in the Subwavelength Regime / 3 1.3 Impact of Variability on Yield and Performance / 5 1.4 Industry Challenge: The Disappearing Process Window / 9 1.5 Mobility Enhancement Techniques: A New Source of Variability I nduced by Design–Process Interaction / 10 1.6 Design Dependency of Chip Surface Topology / 12 1.7 Newly Exacerbated Narrow Width Effect in Nano-CMOS Nodes / 12 1.8 Well Proximity Effect / 14 1.9 Need for Model-Based DFM Solutions Beyond 65 nm / 15 1.10 Summary / 16 References / 16 I NEWLY EXACERBATED EFFECTS 19 2 Lithography-Related Aspects of DFM 21 2.1 Economic Motivations for DFM / 21 2.2 Lithographic Tools and Techniques for Advanced Technology Nodes / 27 2.2.1 Lithographic Approaches to Sub-90-nm Lithography / 27 2.2.2 Lithographic Infrastructure / 27 2.2.3 Immersion Exposure Tools / 32 v vi CONTENTS 2.2.4 Overlay / 39 2.2.5 Cooptimization of the Mask, the Illuminator, and Apodization / 42 2.2.6 Optical Proximity Correction / 54 2.2.7 Double Patterning / 58 2.2.8 Lithographic Roadmap / 63 2.3 Lithography Limited Yield / 65 2.3.1 Deviations of Printed Shape from Drawn Polygon / 65 2.3.2 Increased Variabilities / 67 2.3.3 Catastrophic Failures / 82 2.4 Lithography-Driven DFM Solutions / 85 2.4.1 Practical Boundary Conditions for DFM / 85 2.4.2 Classical Approach / 88 2.4.3 Printability Checkers / 90 2.4.4 Model-Based Design Rule Checks / 96 2.4.5 ASIC Cell Optimizations / 100 2.4.6 Lithography-Aware Routers / 105 2.4.7 Advanced OPC Techniques for Improved Manufacturing / 108 References / 122 3 Interaction of Layout with Transistor Performance and Stress Engineering Techniques 126 3.1 Introduction / 126 3.2 Impact of Stress on Transistor Performance / 127 3.2.1 Electron Mobility / 128 3.2.2 Hole Mobility / 129 3.2.3 Threshold Voltage / 131 3.2.4 Junction Leakage / 140 3.2.5 High Stress Levels / 144 3.2.6 Crystal Orientations / 147 3.2.7 Uniaxial, Biaxial, and Arbitrary Stress Patterns / 149 3.2.8 Stress Gradients / 151 3.2.9 Effects of Temperature and High Dopant Concentrations / 152 3.2.10 Stress Effects in Nonsilicon Semiconductors / 152 3.3 Stress Propagation / 153 3.3.1 Stress Propagation for Various Stress Source Geometries / 153 3.3.2 Stress Propagation Through STI and Other Barriers / 154 3.3.3 Free Boundaries / 155 CONTENTS vii 3.4 Stress Sources / 156 3.4.1 Thermal Mismatch: STI and Silicide / 156 3.4.2 Lattice Mismatch: eSiGe and Si : C / 159 3.4.3 Layer Growth / 161 3.4.4 Intrinsic Stress: CESL and DSL / 162 3.4.5 Stress Memorization Technique / 165 3.4.6 Stress Measurement Techniques / 165 3.4.7 Stress Simulation Techniques / 167 3.5 Introducing Stress into Transistors / 170 3.5.1 Stress Evolution During Process Flow / 171 3.5.2 Stress Relaxation Mechanisms / 172 3.5.3 Combining Several Stress Sources / 173 3.5.4 Stress-Engineered Memory Retention / 174 3.5.5 Layout-Induced Variations / 174 3.5.6 Bulk Transistors versus SOI and FinFET / 179 References / 181 II DESIGN SOLUTIONS 185 4 Signal and Power Integrity 187 4.1 Introduction / 187 4.2 Interconnect Resistance, Capacitance, and Inductance / 189 4.2.1 Process Scaling and Interconnect Fabrication / 189 4.2.2 Impact of Process Scaling on Resistance and Capacitance / 191 4.2.3 Scaling and Reliability / 194 4.2.4 Interconnect Delay, Energy, and Scaling Implications / 197 4.3 Inductance Effects on an Interconnect / 200 4.3.1 Emergence of Inductance as a Limiting Characteristic on Signal Integrity / 200 4.3.2 Inductance Simulation and Extraction / 202 4.3.3 Inductance-Infl uenced (RLC) Signal Delay / 206 4.3.4 Single-Line Delay Considerations / 207 4.3.5 Delay and Crosstalk for Buses / 209 4.3.6 Optimized Bus Design / 211 4.3.7 Clock Line Design / 213 4.3.8 Power Grid Design / 229 References / 253 viii CONTENTS 5 Analog and Mixed-Signal Circuit Design for Yield and Manufacturability 256 5.1 Introduction / 256 5.2 Device Selection / 256 5.3 “Heartbeat” Device Size / 259 5.4 Device Matching / 260 5.4.1 Shallow Trench Isolation / 260 5.4.2 Well Proximity Effects / 261 5.4.3 Poly Gate Variation / 264 5.5 Design Guidelines / 267 5.5.1 Simulation Methodology / 267 5.5.2 Monte Carlo Analysis / 272 5.5.3 Device Confi guration / 274 5.6 Layout Guidelines / 274 5.6.1 Analog Layout Design Rules / 275 5.6.2 Floor Planning / 276 5.6.3 Power Busing / 277 5.6.4 Signal Routing / 278 5.6.5 Dummy Diffusion–Poly–Metal / 279 5.7 Testing / 280 References / 280 6 Design for Variability, Performance, and Yield 281 6.1 Introduction / 281 6.2 Impact of Variations on Design / 282 6.2.1 Impact of Variation on Bitcell Design / 282 6.2.2 Impact of Variation on Analog Circuits / 286 6.2.3 Impact of Variation on Digital Circuits / 287 6.3 Some Parametric Fluctuations with New Implications for Design / 289 6.3.1 Random Dopant Fluctuations / 289 6.3.2 Line-Edge Roughness Impact on Leakage / 291 6.3.3 Poly Critical Dimension Uniformity and Oxide Thickness Variation / 292 6.3.4 Stress Variation of Straining Film and eSiGe with Different Contexts / 296 6.4 Process Variations in Interconnects / 299 6.5 Impact of Deep-Submicron Integration in SRAMs / 303 6.6 Impact of Layout Styles on Manufacturability, Yield, and Scalability / 304 6.6.1 Insuffi ciency of Meeting Design Rules Alone / 304 6.6.2 Wire Uniformity and Density; High Diffusion Density / 308 CONTENTS ix 6.6.3 Minimum-Spaced Wire over Wide Metals / 308 6.6.4 Misaligment Issues Coupled with Poly Corner Rounding and Diffusion Flaring / 309 6.6.5 Well Corner Rounding Issues / 312 6.6.6 OPC and OPC Reproducibility / 312 6.6.7 Timing Implications of Cell Mirroring / 313 6.6.8 Mask Cost, Complexity, and Building Throughput Time / 313 6.7 Design for Variations / 316 6.7.1 Limiting the Degrees of Freedom to Improve Design Uniformity / 316 6.7.2 Stress Proximity Extraction / 319 6.7.3 Contour-Based Extraction: Design in the Era of Lithographic Distortion / 321 6.7.4 Design Compensation for Variations / 322 6.7.5 Layout Optimization to Maximize Useful Stress and Reduce Variability / 324 6.8 Summary / 330 References / 331 III THE ROAD TO DFM 333 7 Nano-CMOS Design Tools: Beyond Model-Based Analysis and Correction 335 7.1 Introduction / 335 7.2 Electrical Design for Manufacturability / 337 7.2.1 Library Preparation Methodology / 340 7.2.2 Leakage Optimization Methodology / 341 7.3 Criticality-Aware DFM / 343 7.3.1 Defi nition of Criticalities / 343 7.3.2 Applications of the Criticality-Aware Approach / 344 7.3.3 Automatic Layout Optimization Flow / 345 7.3.4 Optimizing the Layout / 348 7.3.5 Examples of Cost Function Trade-offs / 351 7.3.6 Criticality-Aware Layout Optimization Summary / 354 7.4 On Guardbands, Statistics, and Gaps / 355 7.4.1 Time Constants and the Inevitability of Guardbanding / 356 7.4.2 Practicality and the Value of Statistical Design / 358 7.4.3 Gaps in Nascent Flows / 358 x CONTENTS 7.5 Opportunistic Mindsets / 360 7.5.1 The CORR Methodology / 361 7.5.2 Auxiliary Pattern for Cell-Based OPC / 364 nduced by Design–Process Interaction / 10 1.6 Design Dependency of Chip Surface Topology / 12 1.7 Newly Exacerbated Narrow Width Effect in Nano-CMOS Nodes / 12 1.8 Well Proximity Effect / 14 1.9 Need for Model-Based DFM Solutions Beyond 65 nm / 15 1.10 Summary / 16 References / 16 I NEWLY EXACERBATED EFFECTS 19 2 Lithography-Related Aspects of DFM 21 2.1 Economic Motivations for DFM / 21 2.2 Lithographic Tools and Techniques for Advanced Technology Nodes / 27 2.2.1 Lithographic Approaches to Sub-90-nm Lithography / 27 2.2.2 Lithographic Infrastructure / 27 2.2.3 Immersion Exposure Tools / 32 v vi CONTENTS 2.2.4 Overlay / 39 2.2.5 Cooptimization of the Mask, the Illuminator, and Apodization / 42 2.2.6 Optical Proximity Correction / 54 2.2.7 Double Patterning / 58 2.2.8 Lithographic Roadmap / 63 2.3 Lithography Limited Yield / 65 2.3.1 Deviations of Printed Shape from Drawn Polygon / 65 2.3.2 Increased Variabilities / 67 2.3.3 Catastrophic Failures / 82 2.4 Lithography-Driven DFM Solutions / 85 2.4.1 Practical Boundary Conditions for DFM / 85 2.4.2 Classical Approach / 88 2.4.3 Printability Checkers / 90 2.4.4 Model-Based Design Rule Checks / 96 2.4.5 ASIC Cell Optimizations / 100 2.4.6 Lithography-Aware Routers / 105 2.4.7 Advanced OPC Techniques for Improved Manufacturing / 108 References / 122 3 Interaction of Layout with Transistor Performance and Stress Engineering Techniques 126 3.1 Introduction / 126 3.2 Impact of Stress on Transistor Performance / 127 3.2.1 Electron Mobility / 128 3.2.2 Hole Mobility / 129 3.2.3 Threshold Voltage / 131 3.2.4 Junction Leakage / 140 3.2.5 High Stress Levels / 144 3.2.6 Crystal Orientations / 147 3.2.7 Uniaxial, Biaxial, and Arbitrary Stress Patterns / 149 3.2.8 Stress Gradients / 151 3.2.9 Effects of Temperature and High Dopant Concentrations / 152 3.2.10 Stress Effects in Nonsilicon Semiconductors / 152 3.3 Stress Propagation / 153 3.3.1 Stress Propagation for Various Stress Source Geometries / 153 3.3.2 Stress Propagation Through STI and Other Barriers / 154 3.3.3 Free Boundaries / 155 CONTENTS vii 3.4 Stress Sources / 156 3.4.1 Thermal Mismatch: STI and Silicide / 156 3.4.2 Lattice Mismatch: eSiGe and Si : C / 159 3.4.3 Layer Growth / 161 3.4.4 Intrinsic Stress: CESL and DSL / 162 3.4.5 Stress Memorization Technique / 165 3.4.6 Stress Measurement Techniques / 165 3.4.7 Stress Simulation Techniques / 167 3.5 Introducing Stress into Transistors / 170 3.5.1 Stress Evolution During Process Flow / 171 3.5.2 Stress Relaxation Mechanisms / 172 3.5.3 Combining Several Stress Sources / 173 3.5.4 Stress-Engineered Memory Retention / 174 3.5.5 Layout-Induced Variations / 174 3.5.6 Bulk Transistors versus SOI and FinFET / 179 References / 181 II DESIGN SOLUTIONS 185 4 Signal and Power Integrity 187 4.1 Introduction / 187 4.2 Interconnect Resistance, Capacitance, and Inductance / 189 4.2.1 Process Scaling and Interconnect Fabrication / 189 4.2.2 Impact of Process Scaling on Resistance and Capacitance / 191 4.2.3 Scaling and Reliability / 194 4.2.4 Interconnect Delay, Energy, and Scaling Implications / 197 4.3 Inductance Effects on an Interconnect / 200 4.3.1 Emergence of Inductance as a Limiting Characteristic on Signal Integrity / 200 4.3.2 Inductance Simulation and Extraction / 202 4.3.3 Inductance-Infl uenced (RLC) Signal Delay / 206 4.3.4 Single-Line Delay Considerations / 207 4.3.5 Delay and Crosstalk for Buses / 209 4.3.6 Optimized Bus Design / 211 4.3.7 Clock Line Design / 213 4.3.8 Power Grid Design / 229 References / 253 viii CONTENTS 5 Analog and Mixed-Signal Circuit Design for Yield and Manufacturability 256 5.1 Introduction / 256 5.2 Device Selection / 256 5.3 “Heartbeat” Device Size / 259 5.4 Device Matching / 260 5.4.1 Shallow Trench Isolation / 260 5.4.2 Well Proximity Effects / 261 5.4.3 Poly Gate Variation / 264 5.5 Design Guidelines / 267 5.5.1 Simulation Methodology / 267 5.5.2 Monte Carlo Analysis / 272 5.5.3 Device Confi guration / 274 5.6 Layout Guidelines / 274 5.6.1 Analog Layout Design Rules / 275 5.6.2 Floor Planning / 276 5.6.3 Power Busing / 277 5.6.4 Signal Routing / 278 5.6.5 Dummy Diffusion–Poly–Metal / 279 5.7 Testing / 280 References / 280 6 Design for Variability, Performance, and Yield 281 6.1 Introduction / 281 6.2 Impact of Variations on Design / 282 6.2.1 Impact of Variation on Bitcell Design / 282 6.2.2 Impact of Variation on Analog Circuits / 286 6.2.3 Impact of Variation on Digital Circuits / 287 6.3 Some Parametric Fluctuations with New Implications for Design / 289 6.3.1 Random Dopant Fluctuations / 289 6.3.2 Line-Edge Roughness Impact on Leakage / 291 6.3.3 Poly Critical Dimension Uniformity and Oxide Thickness Variation / 292 6.3.4 Stress Variation of Straining Film and eSiGe with Different Contexts / 296 6.4 Process Variations in Interconnects / 299 6.5 Impact of Deep-Submicron Integration in SRAMs / 303 6.6 Impact of Layout Styles on Manufacturability, Yield, and Scalability / 304 6.6.1 Insuffi ciency of Meeting Design Rules Alone / 304 6.6.2 Wire Uniformity and Density; High Diffusion Density / 308 CONTENTS ix 6.6.3 Minimum-Spaced Wire over Wide Metals / 308 6.6.4 Misaligment Issues Coupled with Poly Corner Rounding and Diffusion Flaring / 309 6.6.5 Well Corner Rounding Issues / 312 6.6.6 OPC and OPC Reproducibility / 312 6.6.7 Timing Implications of Cell Mirroring / 313 6.6.8 Mask Cost, Complexity, and Building Throughput Time / 313 6.7 Design for Variations / 316 6.7.1 Limiting the Degrees of Freedom to Improve Design Uniformity / 316 6.7.2 Stress Proximity Extraction / 319 6.7.3 Contour-Based Extraction: Design in the Era of Lithographic Distortion / 321 6.7.4 Design Compensation for Variations / 322 6.7.5 Layout Optimization to Maximize Useful Stress and Reduce Variability / 324 6.8 Summary / 330 References / 331 III THE ROAD TO DFM 333 7 Nano-CMOS Design Tools: Beyond Model-Based Analysis and Correction 335 7.1 Introduction / 335 7.2 Electrical Design for Manufacturability / 337 7.2.1 Library Preparation Methodology / 340 7.2.2 Leakage Optimization Methodology / 341 7.3 Criticality-Aware DFM / 343 7.3.1 Defi nition of Criticalities / 343 7.3.2 Applications of the Criticality-Aware Approach / 344 7.3.3 Automatic Layout Optimization Flow / 345 7.3.4 Optimizing the Layout / 348 7.3.5 Examples of Cost Function Trade-offs / 351 7.3.6 Criticality-Aware Layout Optimization Summary / 354 7.4 On Guardbands, Statistics, and Gaps / 355 7.4.1 Time Constants and the Inevitability of Guardbanding / 356 7.4.2 Practicality and the Value of Statistical Design / 358 7.4.3 Gaps in Nascent Flows / 358 x CONTENTS 7.5 Opportunistic Mindsets / 360 7.5.1 The CORR Methodology / 361 7.5.2 Auxiliary Pattern for Cell-Based OPC / 364